The packaging of semiconductor components such as power semiconductor devices involves a number of design challenges. Such challenges include cost, heat dissipation, device protection, size, performance, and reliability among others. Examples of prior art power packages that have been developed and improved upon to address such issues include the TO-220, TO-218, CASE 77, TO-247, Dpak, D2pak, D3pak, quad flat pack no-lead (QFN), quad flat pack (QFP), small outline (SOP) packages among others.
Power semiconductor device manufacturers have recently introduced new power device packages that provide heat dissipation paths from both top and bottom surfaces of the package. The dual heat dissipation paths provide, among other things, increased current density compared to conventional single dissipation path packages, and improved junction-to-ambient thermal impedance. In addition, the dual heat dissipation path packages can either handle more power or operate with a lower junction temperature compared to single heat dissipation path packages. A lower junction temperature means a lower drain to source on-resistance for MOSFET devices, which in turn provides a higher efficiency packaged component. A reduction in junction temperature means an increase in product reliability.
Although the new dual heat dissipation path packages provide some operating advantages compared to other prior art packages, several manufacturing challenges still exist that prevent these packages from being optimally reliable and cost effective. Such challenges include exposed semiconductor die surfaces, inconsistent alignment of piece parts and components, non-standard piece part designs that require expensive assembly tool modifications, and the need for component masking and shimming steps.
Accordingly, a need exists for a package structure and method of manufacture that addresses these specific challenges as well as others.
For ease of understanding, elements in the drawing figures are not necessarily drawn to scale, and like element numbers are used where appropriate throughout the various figures to denote the same or similar elements. Although the present invention is described below in a power transistor configuration having three electrodes, those skilled in the art understand that the present invention is applicable to other semiconductor devices as well.